1. Field of the Invention
The present invention relates to the fabrication of integrated circuits, and, more particularly, to the implanting of ions of dopant materials into workpieces and/or substrates suitable for the fabrication of integrated circuits. More specifically, the present invention relates to a method of forming a strained surface layer into substrates during the fabrication of field effect transistors.
2. Description of the Related Art
In the last several years, the number of circuit elements manufactured on semiconductor substrates has continuously grown, and accordingly the size of circuit elements commonly fabricated has continuously decreased. Moreover, modern manufacturing technologies have developed so as to include several ion implanting steps. For instance, ion implanting steps are currently performed for the purpose of forming well structures, halo structures, source and drain regions, and the like. However, as the miniaturization of the circuit elements has developed, the need has arisen to restrict the doping profiles of the various implants within well-defined locations. That is, implantations need to be confined within regions of the substrate having dimensions in conformity with the reduced feature sizes of the circuit elements, e.g., transistors, to be formed. To obtain the shallow doping profiles required, all physical mechanisms allowing dopants to penetrate deeper into the substrate must be strictly controlled or eliminated. One important factor to be controlled is ion channeling. To accomplish this end, shallow profile doping processes often use a so-called xe2x80x9cpre-amorphizationxe2x80x9d implantation step prior to the actual dopant implantations. In particular, an amorphous zone is usually formed during a first pre-amorphization implantation, and, during subsequent implantation processes, the doped regions (halo and source/drain regions) are formed. Commonly, heavy inert ions like germanium or xenon are implanted at an implant energy of approximately 80-200 keV.
In the following, a brief description will be given with reference to FIGS. 1a-1c of a typical prior art process for forming the active regions of a field effect transistor, including a typical xe2x80x9cpre-amorphizationxe2x80x9d implanting step.
FIG. 1a schematically shows a MOS transistor 100 to be formed on a substrate 1, such as a silicon wafer. Isolation structures 2 define an active region of the transistor 100. Moreover, reference 3 relates to a polysilicon gate electrode of the MOS transistor 100. Finally, reference 6 denotes a gate insulation layer.
In FIGS. 1b-1c, those parts already described with reference to FIG. 1a are identified by the same reference numerals. In addition, in FIG. 1b, reference 7a relates to an ion beam to which the substrate 1 is exposed during a xe2x80x9cpre-amorphizationxe2x80x9d implanting process, and reference 5a relates to amorphous regions formed into the substrate 1.
FIG. 1c shows the MOS transistor 100 once the active regions have been completed. In particular, in FIG. 1c, reference 5h relates to halo regions formed into the substrate and references 5S and 5D identify the source and drain regions of the transistor 100, respectively. Moreover, in FIG. 1c, reference 4 relates to dielectric sidewall spacers formed on the sidewalls of the polysilicon line 3.
A typical process flow for forming the active regions of the transistor 100 comprising the amorphous regions 5a, the halo structures 5h and the source and drain regions 5S and 5D may be summarized as follows.
Following the formation of the gate insulation layer 6 and the overlying polysilicon line 3 according to well known lithography and etching techniques (see FIG. 1a), the amorphous regions 5a are formed during a first implant-step (see FIG. 1b). To this end, the substrate 1 is exposed to an ion beam 7a and heavy-ions such as, for example, phosphorous, arsenic, and argon are implanted into the substrate at an implanting energy of about 80 keV.
Once the amorphous regions 5a have been formed as described above, the manufacturing process is resumed, and several further implanting steps are carried out for the purpose of forming the halo structures 5h and the source and drain regions 5S and 5D. In particular, during a so-called halo implanting step, boron ions in NMOS transistors and phosphorous ions in PMOS transistors are implanted at 90 keV with a dose of 2xc3x971013 cmxe2x88x922. After forming the halo structures 5h, a subsequent implanting step is carried out for forming the source and drain extension regions (not shown) of the transistor 100. To this end, a dose of approximately 3xc3x971013-3xc3x971014 cmxe2x88x922 dopant ions is implanted at low energy (30-50 keV). Similar to the halo implantation step, this implantation step causes the edges of the implanted regions to be substantially aligned with the edge of the gate insulation layer 6. Subsequently, dielectric sidewall spacers 4 are formed on the sidewalls of the polysilicon line 3 according to well known techniques, and a further heavy implantation step is carried out for implanting dopants into those regions of the substrate not covered by the polysilicon line 3 and the sidewall spacers 4. At the end of the heavy implantation step, the source and drain regions 5S and 5D are formed to exhibit the desired concentration.
The prior art manufacturing process as depicted above is affected by several drawbacks. For instance, the mobility in the channel region, i.e., in the portion of the substrate underlying the gate insulation layer 6 and between the source and drain regions 5S and 5D, is too low when compared to the high speed and high performance required in modern transistors. Moreover, damage results in the substrate in proximity to the source-drain junction during the pre-amorphization implanting step as depicted in FIG. 1b so that leakage currents may arise, leading to malfunctioning of the transistor.
Many efforts have been made and several solutions have been proposed in the art to overcome at least some of these drawbacks. In particular, it has been proposed to improve the mobility of the electrical charges in the channel region by forming a strained surface layer on the; substrate at the beginning of the manufacturing process, i.e., before forming the polysilicon structure 3 and before the usual implanting steps are carried out. In the following, a description will be given with reference to FIGS. 2a-2d of a typical prior art process for forming the active regions of a field effect transistor, including a typical step for generating a strained surface layer on the substrate.
FIG. 2a schematically shows a substrate 1, such as a silicon wafer, on which a MOS transistor is to be formed. Isolation structures 2 define an active region of the transistor 100. Moreover, reference 1e identifies a strained layer that is formed on the surface of the substrate 1, as will be described in the following. In the particular example depicted in FIG. 2a, it is assumed that the strained layer 1e is formed after formation of the isolation structures 2. However, processes are known in the art according to which the strained layer 1e is formed first and the isolation structures 2 are formed thereafter.
In FIGS. 2b-2c, those parts already described with reference to FIGS. 2a and 1a-1c are identified by the same reference numerals. Accordingly, reference 7a in FIG. 2b identifies an ion beam to which the substrate 1 is exposed for the purpose of forming amorphous regions 5a. Moreover, in FIG. 2b, reference 6 relates to a gate insulation layer and reference 3 relates to a polysilicon line formed thereon. Finally, in FIG. 2c, reference 4 relates to sidewall spacers formed on the sidewalls of the polysilicon line 3, while the references 5h, 5S and 5D identify halo structures and source and drain regions of the transistor 100, respectively. The polysilicon line 3, the gate insulation layers 6, the halo structures 5h and the source and drain regions 5S and 5D may be formed according to the method steps already described with reference to FIGS. 1a-1c. In the same way, the sequence of these process steps may be the same as described with reference to FIGS. 1a-1c. 
The prior art process for forming a transistor as depicted in FIGS. 2a-2c starts with the formation of a strained surface layer 1e on the surface of the substrate 1 (see FIG. 2a). To this end, a silicon layer is epitaxially grown on a relaxed Silxe2x88x92xGex (not shown) previously formed on the surface of the silicon substrate 1. However, the relaxed Silxe2x88x92xGex layer is formed by intentionally alloying the initially deposited silicon with germanium. Since the Sixe2x80x94Ge alloy has a substantially different lattice parameter than the substrate, a strained layer is formed on the surface of the substrate with relaxed Silxe2x88x92xGex. In addition to the energy band splitting associated with the vertical electric field in the MOS structure, the strain induces an energy splitting, xcex94Esxcx9c67 meV/10% Ge, associated with the crystal asymmetry, increasing the overall splitting xcex94Etot between the perpendicular (xcex942) and parallel (xcex944) conduction bands. The resulting re-population of the energy bands produces enhancement of the low field effective electron mobility xcexceff.
Once the strained surface layer 1e has been formed, the transistor 100 is completed according to the usual manufacturing techniques. In particular, a gate insulation layer is formed on the substrate 1 and patterned according to well-known masking and etching techniques so as to form the gate insulation structure 6. Subsequently, the polysilicon line 3 is formed on the gate insulation structure 6 still according to well-known depositing, patterning, and etching techniques. Finally, once the polysilicon gate structure has been formed, the manufacturing process is prosecuted as substantially depicted with reference to FIGS. 1b-1c so as to form the active regions of the transistor 100 of FIG. 2c, comprising halo structures 5h and source and drain regions 5S and 5D, with sidewall spacers 4 being formed on the sidewalls of the polysilicon gate structure. However, at the end of the manufacturing process, the transistor will comprise a strained layer 1e in the channel region, i.e., in the region of the transistor underlying the gate insulation layers 6 and between the source and drain regions 5S and 5D (see FIG. 2c). As stated above, it is considered that the strained layer 1e exhibits an improved mobility of the electrical charges in the channel region, so that a higher switching speed and improved electrical performances of the transistor may be obtained.
However, the generation of a strained surface layer 1e as depicted above is quite troublesome and expensive, and as such cannot be easily implemented in a production process. In fact, complex machinery is required for epitaxially growing the Sixe2x80x94Ge strained surface layer 1e and the process parameters have to be attentatively controlled, otherwise crystalline defects, such as misfit dislocations, could be generated which could negatively affect the functioning of the transistor.
Accordingly, in view of the problems explained above, it would be desirable to provide a technique that may solve or at least reduce one or more of these problems. In more detail, it would be desirable to provide a technique that improves the mobility in the channel region of a field effect transistor, thus improving the switching speed and the electrical performance of the transistor. In particular, it would be desirable to provide a simple technique that creates a very homogenous strained layer on the surface of a substrate.
In general, the present invention is based on the consideration that field effect transistors exhibiting improved performance can be fabricated when, in addition to the conventional processing steps, a strained surface layer is generated by implanting heavy inert ions into the substrate. In particular, the present invention is based on the consideration that a very homogenously strained layer exhibiting a mobility at least as good as the mobility exhibited by epitaxially grown prior art layers may be obtained by implanting xenon and/or other large, heavy and inert ions into the substrate. Once such a strained layer has been generated, the transistor may be completed according to well-known prior art techniques. However, at the end of the manufacturing process, the transistor will exhibit a switching speed and electrical performance that are at least as good as the switching speed and electrical performance exhibited by a transistor comprising an epitaxial strained layer.
According to one embodiment, the present invention relates to a method of forming at least one field effect transistor on a semiconductive substrate comprising generating a strained surface layer on a surface of the substrate by implanting ions of at least one heavy inert material through the surface of the substrate. The method further comprises forming at least one gate structure above the strained surface layer.
According to another embodiment, the present invention relates to a method of forming at least one field effect transistor on a semiconductive substrate comprising forming an insulating film on a surface of the substrate and generating a strained surface layer at the interface of the insulating film and the substrate by implanting ions of at least one heavy inert material through the insulating film into the substrate. The method further comprises forming a gate insulating structure.